1. Field of the Invention
The present invention generally relates to delay-lock-loop circuits, and more particularly to a delay-lock-loop circuit with an adjustable delay chain that does not require a digital to analog converter.
2. Description of the Related Art
Delay-lock-loop (DLL) circuits can be used to create, control, or modify clock signals, either within a semiconductor device or between several semiconductor components. FIG. 1 demonstrates a first clock signal (KCLK) and three additional clock signals (KCLKB, KCLKC, and KCLKD), which have been derived from the first clock. In this example, the derived clocks have been phase shifted from the first clock by 90°, 180°, and 270°, respectively. One application for these derived clocks is to synchronize different components within a system by providing specific clock edges for each component. Data signals that are aligned with the first clock signal, and transition on both the rising and falling edges of the first clock, can be sampled by another circuit or component by clock signals KCLKB and KLCKD, respectively. These clock signals have been phase shifted by 90° from the rising and falling edges, such that they will be exactly positioned between the transitions of the aligned data signal and will sample the data in the middle of the data valid window.
Creating, controlling, and modifying clock signals with a DLL circuit has been the subject of conventional devices. The basic premise behind the DLL circuit is to provide an adjustable delay circuit that can be tuned to match the frequency of a supplied clock signal, and then using this tuned delay to create the modified clock signals. Once a circuit element is tuned to match the base clock, it is relatively straightforward to derive phase shifted clocks, delayed clocks, or clocks that operate at a multiple of the supplied clocks' frequency.
FIG. 2 shows an example of a prior art DLL design, wherein a clock signal 100 is received by clock buffer 101 which generates internal clock CLKIN 110. The internal clock drives into the delay circuit 120, which is comprised of individual delay elements 121. In this instance, the individual delay elements 121 are comprised of two inverters, or the minimum digital delay element for the given technology. Outputs from each stage of the delay chain (da, db, dc, dn) are fed into a logic block known as a mux (multiplexer) tree 150, which is used to steer a specific delay value to the appropriate phase vectors 155. The number of delay elements required for each phase is determined by comparing the original clock input 110 to the desired phase vector 135 for 360° with the phase compare logic 130. The mux tree controls 140 receives the output of the phase comparator and then adjusts the mux tree inputs depending on whether more, or fewer, delay elements are needed to be able to match the incoming clock frequencies.
Prior art DLL circuits designed in the manner of FIG. 2 suffer from several problems, most of which relate to the minimum delay step. Because this style of DLL uses fixed delay elements, the accuracy of the phase alignment is limited to this minimum delay. Known as clock jitter, the error in accurately reproducing phase vectors directly limits the maximum frequency of a given system. Even with advanced technologies the minimum delay element might be in the order of 20 ps, a significant amount when designing a clock that might need to capture data within a 200 ps window. Using these advanced technologies at slower cycles reveals another problem with this style of DLL; the large number of minimum delay elements required to match the lower frequency and the resulting complexity of the mux tree and mux tree logic. As the mux tree grows, it becomes increasingly difficult to match all paths through the tree, and therefore clock jitter worsens.
To eliminate the shortcomings inherent with the fixed delay element style of DLL (FIG. 2) an analog approach has been proposed in U.S. Pat. No. 6,125,157 issued to Donnelly et. al., further illustrated in FIG. 3, wherein a block diagram of this DLL approach is given. A number of adjustable analog delay circuits 210 replace the fixed delay elements. In this approach four adjustable delay circuits are used to provide four clock phases. In practice, any number of delay elements can be used to provide any number of additional clock phases. Only the output from the last adjustable delay circuit Phase 360° is used to compare with the incoming clock 215 at the phase comparator 220.
Moreover, the mux tree has been eliminated. In this DLL style, the delay chain is essentially stretched and compressed by controlling the delay through each of the analog delay elements until the output from the last delay element (Phase 360o) aligns with the incoming clock. The analog delay elements will vary by a very small amount compared with the fixed digital delay element (basically two inverters) and the complex mux logic has been eliminated. In place of the mux logic is a digital to analog converter 250 which must translate the digital output from the phase comparator and counter control 240 to analog signals. The digital to analog converter (DAC) will vary the current to each of the analog delay elements, therefore varying the amount of delay. Although this analog approach to the DLL circuit solves some of the aforementioned problems it has drawbacks of its own. Analog circuits are more complex than digital ones and are difficult to scale from one technology to another, especially at reduced voltages. Also, analog circuits consume more design resources than purely digital designs and are therefore very costly. Therefore, there is a need for a novel digital DLL circuit with an adjustable delay chain that does not require a digital to analog converter (DAC).